Abstract

A Survey: On Various Placers Used in VLSI Standard Cell Placement and Mixed Cell Placement

Author(s): M. Shunmugathammal, C. Christopher Columbus and S. Anand

The placement technique is to place modules into a fixed outline rectangular die in that, no modules should not overlap with each other and some cost effective parameter (e.g., wire length) is optimized. Placement is an important step in VLSI physical design process. Generally placement algorithms (called placers) can be classified into three major categories: simulated annealing based placers, min-cut based placers, and analytical based placers. According to the recent literature, analytical placers give the best quality in placement in VLSI physical design step. Analytical placers are further classified into two types (i) nonlinear (ii) quadratic. Again quadratic placers are further classified into three types (i) partitioning based quadratic placers (ii) Force directed quadratic placers (iii) Warping based quadratic placers. In this paper, we take a brief survey about the various analytical quadratic force directed placers. This survey paper first introduces the placement problem and then how that placement problem is solved using various techniques in analytical quadratic force directed placement are explained. Finally this paper explains bench marking in various analytical force directed placers in standard cell placement and mixed cell placement and also gives some suggestions for future work.